Purchase HM5425801B, In-stock HM5425801B From SeekIC.
Part Number: HM5425801B
Description: The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operatio...
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HM5425801B
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DataSheet
General Description
HM5425801B General Description
The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK . This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
HM5425801B Maximum Ratings
| Parameter | Symbol | Value | Unit | Note |
| Supply voltage relative to VSS | VCC, VCCQ | 1.0 to +3.6 | V | |
| Voltage on inputs pin relative to Vss | Vti | 1.0 to +3.6 | V | |
| Voltage on I/O pins relative to VSS | VTio | 0.5 to +3.6 | V | |
| Short circuit output current | Iout | 50 | mA | |
| Power dissipation | PT | 1.0 | W | |
| Operating temperature | Topr | 0 to +70 | ||
| Storage temperature | Tstg | -55 to +125 |
HM5425801B Features
• 2.5 V power supply
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 143 MHz/133 MHz/125 MHz/100 MHz (max)
• Data inputs, outputs, and DM are synchronized with DQS
• 4 banks can operate simultaneously and independently
• Burst read/write operation
• Programmable burst length: 2/4/8
--Burst read stop capability
• Programmable burst sequence
--Sequential
--Interleave
• Start addressing capability
--Even and Odd
• Programmable CAS latency: 2/2.5
• 8192 refresh cycles: 7.8 s (64 ms/8192 cycles)
• 2 variations of refresh
--Auto refresh
--Self refresh
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 143 MHz/133 MHz/125 MHz/100 MHz (max)
• Data inputs, outputs, and DM are synchronized with DQS
• 4 banks can operate simultaneously and independently
• Burst read/write operation
• Programmable burst length: 2/4/8
--Burst read stop capability
• Programmable burst sequence
--Sequential
--Interleave
• Start addressing capability
--Even and Odd
• Programmable CAS latency: 2/2.5
• 8192 refresh cycles: 7.8 s (64 ms/8192 cycles)
• 2 variations of refresh
--Auto refresh
--Self refresh
HM5425801B Connection Diagram
HM5425801BTT-10
PDF/DataSheet Download
- Datasheet: HM5425801BTT-10
- File Size: 501458 KB
- Manufacturer: ELPIDA [Elpida Memory]
- Click here to Download
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HM5425801B Relative Products
HM5425401B
The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK . This high speed data transfer is realized by the 2-bit prefetch piplined arch...
HM5425161B
The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK . This high speed data transfer is realized by the 2-bit prefetch piplined arch...
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The HM538253B/HM538254B is a 2-Mbit multiport video RAM equipped with a 256-kword × 8-bit dynamic RAM and a 512-word × 8-bit SAM (full-sized SAM). Its RAM and SAM operate independently and asynchronously. The HM538253B/HM538254B is upwardly compatible with t...
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