HY57V161610ET-I

Features: Single 3.0V to 3.6V power supplyAll device pins are compatible with LVTTL interfaceJEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitchAll inputs and outputs referenced to positive edge of system clockData mask function by UDQM/LDQMInternal two banks operation Auto refresh and ...

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SeekIC No. : 004368229 Detail

HY57V161610ET-I: Features: Single 3.0V to 3.6V power supplyAll device pins are compatible with LVTTL interfaceJEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitchAll inputs and outputs referenced to positive...

floor Price/Ceiling Price

Part Number:
HY57V161610ET-I
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/2/22

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Product Details

Description



Features:

Single 3.0V to 3.6V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin
   pitch
All inputs and outputs referenced to positive edge of system
   clock
Data mask function by UDQM/LDQM
Internal two banks operation

Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
 - 1, 2, 4, 8 and Full Page for Sequence Burst
 - 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 1, 2, 3 Clocks




Pinout

  Connection Diagram


Specifications

Parameter Symbol Rating Unit
Ambient Temperature TA -40 ~ 85 °C
Storage Temperature TSTG -55 ~ 125 °C
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD relative to VSS VDD -1.0 ~ 4.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD 1 W
Soldering Temperature`Time TSOLDER 260`10  `Sec



Description

THE Hynix HY57V161610ET-I is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic appli- cations which require large memory density and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16.

HY57V161610ET-I is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

HY57V161610ET-I Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initi- ated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)




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