HY5DU561622EFP-D43C

The HY5DU561622EFP-D43C is one member of the HY5DU561622EFP family which designed as the 268,435,456-bit CMOS Double Data Rate(DDR) Synchron-ous DRAM that ideally suited for the main memory applications which requires large memory density and high bandwidth. This kind of DDR SDRAM must be powered up and initialized in a predefined manner and the DLL must be enabled for normal operation.

Features of the HY5DU561622EFP-D43C are:(1)lead free (ROHS compliant);(2)full and half strength driver option controlled by EMRS;(3)60 ball FBGA package type;(4)8192 refresh cycles / 64ms;(5)tRAS lock out function supported;(6)auto refresh and self refresh supported;(7)internal four bank operations with single pulsed /RAS;(8)programmable burst length 2/4/8 with both sequential and interleave mode;(9)programmable CAS latency 2/2.5 (DDR200, 266, 333) and 3 (DDR400) supported;(10)DM mask write data-in at the both rising and falling edges of the data strobe;(11)source synchronous-data transaction aligned to bidirectional data strobe (DQS);(12)x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O;(13)on chip DLL align DQ and DQS transition with CK transition.

The absolute maximum ratings of the HY5DU561622EFP-D43C can be summarized as:(1)operating temperature (ambient):0 to 70;(2)storage temper-ature:-55 to 150;(3)voltage on VDD relative to Vss:-1.0 to 3.6 V;(4)voltage on VDDQ relative to Vss:-1.0 to 3.6 V;(5)voltage on inputs relative to Vss:-1.0 to 3.6 V;(6)voltage on I/O pins relative to Vss:-0.5 to 3.6 V;(7)output short circuit current:50 mA;(8)soldering temperature.time:260.10 .sec. If you want to know more information such as the electrical characteristics about the HY5DU561622EFP-D43C, please download the datasheet in www.seekic.com or www.chinaicmart.com .