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HY5DV641622AT-36

Features: • 3.3V for VDD and 2.5V for VDDQ power supply• All inputs and outputs are compatible with SSTL_2 interface• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch• Fully differential clock inputs (CK, /CK) operation• Double data rate interface• Sour...

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SeekIC No. : 004368318 Detail

HY5DV641622AT-36: Features: • 3.3V for VDD and 2.5V for VDDQ power supply• All inputs and outputs are compatible with SSTL_2 interface• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch̶...

HY5DV641622AT-36 Data Sheet

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Part Number:
HY5DV641622AT-36
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/7

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Product Details

Description



Features:

• 3.3V for VDD and 2.5V for VDDQ power supply
• All inputs and outputs are compatible with SSTL_2 interface
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
• Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe


Specifications

 

Parameter

Symbol

Rating

Unit

Ambient Temperature

TA

0 ~ 70

Storage Temperature

TSTG

-55 ~ 125

Voltage on Any Pin relative to VSS

VIN, VOUT

-0.5 ~ 3.6

v

Voltage on VDD relative to VSS

VDD

-0.5 ~ 3.6

v

Voltage on VDDQ relative to VSS

VDDQ

-0.5 ~ 3.6

v

Output Short Circuit Current

IOS

50

mA

Power Dissipation

PD

1

W

Soldering Temperature ⋅ Time

TSOLDER

260`  10

` sec




Description

The Hynix HY5DV641622AT-36 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth.

The Hynix 4Mx16 DDR SDRAMs HY5DV641622AT-36 offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.




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