Features: • High-speed access time: 15, 20, 25 ns• Automatic power-down when chip is deselected• CMOS low power operation- 255 mW (max.) operating- 0.18 mW (max.) CMOS standby• TTL compatible interface levels• Single 3.3V power supply• Fully static operation: no...
IC62LV256L: Features: • High-speed access time: 15, 20, 25 ns• Automatic power-down when chip is deselected• CMOS low power operation- 255 mW (max.) operating- 0.18 mW (max.) CMOS standby̶...
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Features: • High-speed access time: 35, 45, 55, 70 ns• Low active power: 450 mW (typic...
Features: • Access times of 55, 70, 100 ns• CMOS Low power operation: ICC=15mA (typica...

|
Symbol |
Parameter |
Value |
Unit |
|
VTERM |
Terminal Voltage with Respect to GND |
0.5 to +4.6 |
V |
|
TBIAS |
Temperature Under Bias |
55 to +125 |
|
|
TSTG |
Storage Temperature |
65 to +150 |
|
|
PT |
Power Dissipation |
0.5 |
W |
|
IOUT |
DC Output Current (LOW) |
20 |
mA |
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of his specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
The IC62LV256L is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 15 ns maximum.
When CE of the IC62LV256L is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 W (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls oth writing and reading of the memory.
The IC62LV256L is available in the JEDEC standard 28-pin 300mil SOJ and the 8*13.4mm TSOP-1 package.