IDT59920A

The IDT59920A is a high fanout phase lock loop clock driver intended for high performance computing and data-communications applications. The IDT59920A has CMOS outputs.

The IDT59920A maintains Cypress CY7B9920 compatibility while providing two additional features: Synchronous Output Enable (GND/ sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/sOE pin is held low, all outputs are synchronously enabled CY7B9920 compatibility).

However, if GND/sOE is held high, all outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VDDQ/PE is held high, all outputs are synchronized with the positive edge of the REF clock input (CY7B9920 compatibility). When VDDQ/PE is held low, all outputs are synchronized with the negative edge of REF.

The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.