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Part Number: IDT5T905
Description: The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differentia...
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IDT5T905
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DataSheet
General Description
IDT5T905 General Description
The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The IDT5T905 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. Multiple power and grounds reduce noise.
IDT5T905 Maximum Ratings
| Symbol | Description |
Max |
Unit |
| VDD | Power Supply Voltage(2) |
0.5 to +3.6 |
V |
| VDDQ | Output Power Supply(2) |
0.5 to +3.6 |
V |
| VI | Input Voltage |
0.5 to +3.6 |
V |
| VO | Output Voltage(3) |
0.5 to VDDQ +0.5 |
V |
| VREF | Reference Voltage(3) |
0.5 to +3.6 |
V |
| TSTG | Storage Temperature |
65 to +165 |
°C |
| TJ | Junction Temperature |
150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met.
3. Not to exceed 3.6V.
IDT5T905 Features
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion
• High speed propagation delay < 2.5ns. (max)
• Up to 250MHz operation
• Very low CMOS power levels
• 1.5V VDDQ for HSTL interface
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface
• Selectable differential or single-ended inputs and five singleended outputs
• 2.5V VDD
• Available in TSSOP package
• Very low duty cycle distortion
• High speed propagation delay < 2.5ns. (max)
• Up to 250MHz operation
• Very low CMOS power levels
• 1.5V VDDQ for HSTL interface
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface
• Selectable differential or single-ended inputs and five singleended outputs
• 2.5V VDD
• Available in TSSOP package
IDT5T905 Typical Application
• Clock and signal distribution
IDT5T905 Connection Diagram
IDT5T905
PDF/DataSheet Download
- Datasheet: IDT5T905
- File Size: 109561 KB
- Manufacturer: IDT [Integrated Device Technology]
- Click here to Download
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