IDT5T93GL10

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Not to exceed 3.6V.

The IDT5T93GL10 2.5V differential clock buffer is a user-selectable differential input to ten LVDS outputs . The fanout from a differential input to ten LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T93GL10 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock.

The outputs of the IDT5T93GL10 will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications. The IDT5T93GL10 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.