Features: • Phase-lock loop clock distribution for high performance clock tree applications• Output enable bank control• External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal• No external RC network required for PLL loop stability• ...
IDT5V9352: Features: • Phase-lock loop clock distribution for high performance clock tree applications• Output enable bank control• External feedback (FBIN) pin is used to synchronize the out...
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Features: • IDT54/74FCT646 equivalent to FAST™speed;• IDT54/74FCT646A 30% faster...
Features: • IDT54/74FCT646 equivalent to FAST™speed;• IDT54/74FCT646A 30% faster...
Symbol | Description |
Max |
Unit |
VCC | Supply Voltage Range |
0.5 to +3.6 |
V |
VI | Input Voltage |
0.5 toVCC +3.6 |
V |
IIN | Input Current |
±20 |
V |
TSTG | Storage Temperature |
65 to +150 |
°C |
IOUT | DC Output Current |
±50 |
°C |
The IDT5V9352 features three banks of individually configurable outputs. The banks are configured with five, four, and two outputs. The internal divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1. The output frequency relationship is controlled by the fSEL frequency control pins. The fSEL pins, as well as other inputs, are LVCMOS/LVTTL compatible inputs
Unlike many products containing PLLs, the IDT5V9352 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the IDT5V9352 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at REFCLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by setting the PLL_EN to high. The 5V9352 is available in Industrial temperature range (-40°C to +85°C).