IDT5V996

The IDT5V996 is a high fanout PLL based clock driver intended for high performance computing and data-communication applications.

The IDT5V996 has eight programmable skew outputs organized in four banks of two. Skew is controlled by 3-level input signals that may be hard wired to appropriate HIGH-MID-LOW levels. The IDT5V996 provides up to 18 programmable levels of output skew, prescaling, and other features. Other features of IDT5V996 are synchronous output enable (G), TEST, and lock detect indicator (LOCK). When G is held low, all the outputs are synchronously enabled, however, if G is held high, all outputs except 3Q0 and 3Q1 are in the state designated by SE (HIGH or LOW).

When TEST is held low, the chip operates in normal condition. When held high, the PLL is shut off and the chip functions as a buffer. The lock detect indicator asserts high when the phase lock loop has acquired lock. During acquisition, the indicator is in the low state.

Once the PLL has reached the steady-state condition within a specified frequency range, LOCK is asserted high. The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT5V996 has LVTTL outputs with 12mA balanced drive outputs. The IDT5V996 is characterized for operation from 40°C to +85°C.