IS65WV25616ALL

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those  ndicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating  onditions for extended
periods may affect reliability.

The ISSI IS65WV25616ALL/IS65WV25616BLL are highspeed, low power, 4M bit SRAMs organized as 256K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices.

When CS1 is HIGH (deselected) or when CS1 is LOW, and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access.

The IS65WV25616BALL/65WV25616BLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II).