Position: Home  > All Categories> Integrated Circuits (ICs) > K4H510638E-LA2

K4H510638E-LA2

Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe DQS• Four banks operation• Differential clock inputs(CK and CK)• DLL aligns DQ and DQS transition with CK transition• MRS cycle with address key programs -. ...

product image

K4H510638E-LA2 Picture
See larger image
SeekIC No. : 004382775 Detail

K4H510638E-LA2: Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe DQS• Four banks operation• Differential clock inputs(CK and CK)•...

K4H510638E-LA2 Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
K4H510638E-LA2
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/4/26

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe DQS
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
   -. Read latency 2, 2.5 (clock)
   -. Burst length (2, 4, 8)
   -. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package


Pinout

Connection Diagram


Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Undefined Category
VI-B63-IU
X27 589
Motors, Solenoids, Driver Boards/Modules
IHSS57-36-20
ASD-B2-1521-B
Batteries, Chargers, Holders
ICR18650-28A
ICR18650-26F/h
Optical Inspection Equipment
AA924
A21K4B
Isolators
HCPL062N
HCPL316J
Kits
IT243
UVSC-110-4E1
View more