K4H560438E-ZC

Features:

• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA Pb-Free package


Specifications

Parameter	Symbol	Value	Unit
Voltage on any pin relative to VSS	VIN, VOUT	-0.5 ~ 3.6	V
Voltage on VDD & VDDQ supply relative to VSS	VDD, VDDQ	-1.0 ~ 3.6	V
Storage temperature	TSTG	-55 ~ +150	°C
Power dissipation	PD	1.5	W
Short circuit current	IOS	50	mA

Description

The K4H560438E / K4H560838E / is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,785,216 / 4x8,388,608 words by 4/ 8bits, fabricated with SAMSUNG s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.