Purchase K4H560838F-UCCC, In-stock K4H560838F-UCCC From SeekIC.
MFG:SAMSUNG Package Cooled:DIP/SOP D/C:08+
Part Number: K4H560838F-UCCC
MFG: SAMSUNG
Package Cooled: DIP/SOP
D/C: 08+
- Table of contents:
K4H560838F-UCCC
-
Suppliers
DataSheet
General Description
K4H560838F-UCCC Maximum Ratings
|
Parameter |
Symbol |
Value |
Unit |
| Voltage on any pin relative to VSS |
VIN,VOUT |
-0.5 ~ 3.6 |
V |
| Voltage on VDD & VDDQ supply relative to VSS |
VDD,VDDQ |
-1.0 ~ 3.6 |
V |
| Storage temperature |
TSTG |
-55 ~ +150 |
°C |
| Power dissipation |
PD |
1.5 |
W |
| Short circuit current |
IOS |
50 |
mA |
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
K4H560838F-UCCC Features
• 200MHz Clock, 400Mbps data rate.
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Pb-Free package
• RoHS compliant
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Pb-Free package
• RoHS compliant
K4H560838F-UCCC Connection Diagram
K4H560838F-UCCC
PDF/DataSheet Download
- Datasheet: K4H560838F-UCCC
- File Size: 175472 KB
- Manufacturer: SAMSUNG [Samsung semiconductor]
- Click here to Download
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