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Part Number: K4S561633F - X(Z)N
Description: The K4S561633F is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, ...
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K4S561633F - X(Z)N
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General Description
K4S561633F - X(Z)N General Description
The K4S561633F is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
K4S561633F - X(Z)N Maximum Ratings
|
Parameter |
Symbol |
Value |
Unit |
| Voltage on any pin relative to Vss |
VIN, VOUT |
-1.0 ~ 4.6 |
V |
| Voltage on VDD supply relative to Vss |
VDD, VDDQ |
-1.0 ~ 4.6 |
V |
| Storage temperature |
TSTG |
-55 ~ +150 |
°C |
| Power dissipation |
PD |
1.0 |
W |
| Short circuit current |
IOS |
50 |
mA |
K4S561633F - X(Z)N Features
• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 54Balls BOC with 0.8mm ball pitch
( -X : Leaded, -Z : Lead Free).
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 54Balls BOC with 0.8mm ball pitch
( -X : Leaded, -Z : Lead Free).
K4S561633F - X(Z)N Connection Diagram
K4S160822D
PDF/DataSheet Download
- Datasheet: K4S160822D
- File Size: 1211444 KB
- Manufacturer: SAMSUNG [Samsung semiconductor]
- Click here to Download
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- ·K4S161622D
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- 1154685 KB
K4S561633F - X(Z)N Relative Products
K4S561633F - X(Z)L
The K4S561633F - X(Z)L is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design of K4S561633F - X(Z)L allows precise cycle control w...
K4S561633F - X(Z)G
The K4S561633F - X(Z)G is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design of K4S561633F - X(Z)G allows precise cycle control w...
K4S561633F - X(Z)F
The K4S561633F - X(Z)F is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design of K4S561633F - X(Z)F allows precise cycle control w...
K4S561633F - X(Z)E
The K4S561633F - X(Z)E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design of K4S561633F - X(Z)E allows precise cycle control w...
K4S561633F - X(Z)C
The K4S561633F - X(Z)C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design of K4S561633F - X(Z)C allows precise cycle control w...
K4S561633D
The K4S561633D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design of K4S561633D allows precise cycle control with the use of s...
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