K4S64323LF-S(D)S

Features: • 2.5V Power Supply .• LVCMOS compatible with multiplexed address.• Four banks operation.• MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).• EM...

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K4S64323LF-S(D)S Picture
SeekIC No. : 004383060 Detail

K4S64323LF-S(D)S: Features: • 2.5V Power Supply .• LVCMOS compatible with multiplexed address.• Four banks operation.• MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). ...

floor Price/Ceiling Price

Part Number:
K4S64323LF-S(D)S
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/18

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Product Details

Description



Features:

•   2.5V Power Supply .
•   LVCMOS compatible with multiplexed address.
•   Four banks operation.
•   MRS cycle with address key programs.
     -. CAS latency (1 & 2 & 3).
     -. Burst length (1, 2, 4, 8 & Full page).
     -. Burst type (Sequential & Interleave).
•   EMRS cycle with address key programs.
•   All inputs are sampled at the positive going edge of the system clock .
•   Burst read single-bit write operation.
•   Special Function Support.
     -. PASR (Partial Array Self Refresh).
     -. TCSR (Temperature Compensated Self Refresh).
•   DQM for masking.
•   Auto & self refresh.
•   64ms refresh period (4K cycle).
•   Extended temperature range : (-25°C to 85°C).
•   90balls FBGA( -SXXX -Pb, -DXXX -Pb Free).



Specifications

Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 3.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 3.6 V
Storage temperature TSTG -55 ~ +150
Power dissipation PD 1 W
Short circuit current IOS 50 mA



Description

    The K4S64323LF-S(D)S is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG¢s high performance CMOS technology.Synchronous design of K4S64323LF-S(D)S allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle.Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.




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