Purchase K4X56323PG - 7, In-stock K4X56323PG - 7 From SeekIC.
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K4X56323PG - 7
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DataSheet
General Description
K4X56323PG - 7 Maximum Ratings
| Ratings | Symbol |
Value |
Unit |
| Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current |
VIN, VOUT VDD VDDQ TSTG PD IOS |
-0.5 ~ 2.7 -0.5 ~ 2.7 -0.5 ~ 2.7 -55 ~ +150 1.0 50 |
V V V °C W mA |
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
K4X56323PG - 7 Features
• 1.8V power supply, 1.8V I/O power
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
- CAS Latency ( 2, 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
- Partial Self Refresh Type ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
• Internal Temperature Compensated Self Refresh
• Deep Power Down Mode
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• DM0 - DM3 for write masking only.
• Auto refresh duty cycle
- 15.6us for -25 to 85 °C
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
- CAS Latency ( 2, 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
- Partial Self Refresh Type ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
• Internal Temperature Compensated Self Refresh
• Deep Power Down Mode
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• DM0 - DM3 for write masking only.
• Auto refresh duty cycle
- 15.6us for -25 to 85 °C
K4X51323PC-7GC3
PDF/DataSheet Download
- Datasheet: K4X51323PC-7GC3
- File Size: 252897 KB
- Manufacturer: SAMSUNG [Samsung semiconductor]
- Click here to Download
- ·K4X51323PC-7GCA
- SAMSUNG [Samsung semiconductor]
- 16M x32 Mobile-DDR SDRAM
- 252897 KB
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- ·K4X56323PG-7GCA
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