LU3X34FTR Features
4-port, single-chip, integrated physical layer and transceivers for 10Base-T, 100Base-TX, or 100Base-FX functions.
IEEE 802.3 compatible 10Base-T and 100Base-T physical layer interface and ANSI X3.263 TP-PMD compatible transceiver.
Interface support for RMII and SMII switch applications.
Autonegotiation pin configurability on a per-port basis.
FX mode configurable on a per-port basis.
Built-in analog 10 Mbit receive filter, removing the
for external filters.
Built-in 10 bit transmit filter.
10 Mbit PLL, exceeding tolerances for both preamble and data jitter.
100 Mbit PLL, combined with the digital adaptive equalizer, robustly handles variations in rise-fall time, excessive attenuation due to channel loss, duty-cycle distortion, crosstalk, and baseline
wander.
Transmit rise-fall time manipulated to provide lower emissions, amplitude fully compatible for proper
nteroperability.
Programmable scrambler seed for better FCC
compliancy.
IEEE 802.3u Clause 28 compliant autonegotiation for full 10 Mbits/s and 100 Mbits/s control.
Extended management support with interrupt capabilities.
PHY MIB support.
Low-power 500 mA max. - Low-cost 128-pin SQFP packaging with heat spreader.
LU3X34FTR Connection Diagram
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