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Part Number: LU3X54FTL

 

 

 

 

Description: The bused mode has two additional submodes ofoperation:Separate Bused MII Mode. This mode is d...


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LU3X54FTL General Description


The bused mode has two additional submodes of
operation:
Separate Bused MII Mode. This mode is designed to operate with two independent repeater ICs, one repeater operating at 100 Mbits/s and the other operating at 10 Mbits/s.

Figure 6 shows a block diagram of this mode in which separate pins (four of each) are used for COL_10(4), COL_100(4), CRS_10(4), CRS_100(4), RX_EN10(4), RX_EN100(4), TX_EN10 (4), and TX_EN100(4).

The signals RX_CLK10, RXD_10, TX_CLK10, and TXD_10 (all from ports A, B, C, and D) are internally bused together and connected to MII port B. The signals TX_CLK25, TXD_100[3:0], TX_ER, RX_CLK25, RXD_100[3:0], RX_DV, and RX_ER (all
 rom ports A, B, C, D) are internally bused together and connected to MII port A.

The repeater ICs will enable the particular port to which it will communicate by enabling the port with\ TX_EN 10, TX_EN100, RX_EN10, or RX_EN100.

LU3X54FTL Maximum Ratings

Parameter
Min
Symbol
Max
Unit
Ambient Operating Temperature
0
T A
70
°C
Storage Temperature
-40
T stg
125
°C
Power Dissipation
-
P D
3.5
W
Voltage on Any Pin with Respect to Ground
-0.5
-
V DD + 0.5
V
Maximum Supply Voltage
-
-
5.5
V

LU3X54FTL Features

10 Mbits/s Transceiver
Compatible with IEEE * 802.3 10Base-T standard for twisted-pair cable
 Autopolarity detection and correction
Adjustable squelch level for extended line length capability (two levels)
Interfaces with IEEE 802.3u media independent interface (MII) or a serial 10 Mbits/s 7-pin interface
On-chip filtering eliminates the need for external filters
Half- and full-duplex operations

100 Mbits/s TX Transceiver
 Compatible with IEEE 802.3u MII (clause 22), PCS (clause 23), PMA (clause 24), autonegotiation (clause 28), and PMD (clause 25) specifications
Scrambler/descrambler bypass
Encoder/decoder bypass
3-statable MII in 100 Mbits/s mode
Selectable carrier sense signal generation (CRS) asserted during either transmission or reception in half duplex (CRS asserted during reception only in full duplex)
Selectable MII or 5-bit code group interface
Full- or half-duplex operations
Optional carrier integrity monitor (CIM)
On-chip filtering and adaptive equalization that eliminates the need for external filters

LU3X54FTL Connection Diagram

LU3X54FTL  Connection Diagram

LU3X54FTL datasheet

LU3X54FTL
PDF/DataSheet Download

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