M50LPW002

The M50LPW002 is a 2 Mbit (256Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times.

The memory M50LPW002 is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end  of a program or erase operation can be detected  and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The device M50LPW002 features an asymmetrical blocked architecture.
The device has an array of 7 blocks:
· 1 Boot Block of 16 KByte
· 2 Parameter Blocks of 8 KByte each
· 1 Main Block of 32 KByte
· 3 Main Blocks of 64 KByte each
Two different bus interfaces are supported by the memory. The M50LPW002 primary interface is the Low Pin Count (or LPC) Standard Interface. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50LPW002 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.

The M50LPW002 secondary interface, the Address/Address  Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.

The M50LPW002 memory is delivered with all the bits erased (set to 1).