M50LPW012

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to -2V and for less than 20ns during transitions. Maximum Voltage may overshoot to V_CC +2V and for less than 20ns during transitions.

The M50LPW012 is a 2Mbit (256Kb x8) nonvolatile
memory that can be read, erased and
reprogrammed. These operations can be
performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory  contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Two different bus interfaces are supported by the memory. The primary interface is the Low Pin Count (or LPC) Standard Interface. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50LPW012 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.

The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.

The memory is offered in a PLCC32 package and is supplied with all the bits erased (set to 1).

System Memory Mapping
The LPC address sequence is 32 bits long. The M50LPW012 responds to addresses mapped to  the top of the 4 GByte memory space, from FFFF FFFFh. Address bits A31-A24, A22 must be set to 1. A23 is set to 1 for array access, and to 0 for register access.

The M50LPW012 also responds to addresses mapped to the bottom of the 4 GByte memory space, from 0000 0000h. Address bits A31-A24, A22  must be set to 0. A23 is set to 0 for array access, and to 1 for register access.

For A21-A18, see Table 2. A17-A0 are for array addresses.