M58BW032DT

The M58BW032B/D is a 32Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Double-Word basis using a 3.0V to 3.6V VDD supply for the circuit and a VDDQ supply down to 1.6V for the Input and Output buffers.

The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous Bus operations.The Synchronous Burst Read Interface allows a high data transfer rate controlled by the Burst Clock, K, signal. It is capable of bursting fixed or unlimited lengths of data. The burst type,latency and length are configurable and can be
easily adapted to a large variety of system clock frequencies and microprocessors. All Writes are Asynchronous. On power-up the memory defaults to Read mode with an Asynchronous Bus.

The device features an asymmetrical block architecture.The M58BW032B/D has an array of 62 main blocks of 512 Kbits each, plus 4 large parameter blocks of 128Kbits each and 8 small parameter blocks of 64 Kbits each. The large and small parameter blocks are located either at the top (M58BW032BT, M58BW032DT) or at the bottom (M58BW032BB, M58BW032DB) of the address space. The first large parameter block is referred to as Boot Block and can be used either to store a boot code or parameters. The memory array organization is detailed in Tables 2, Top Boot Block Addresses and 3, Bottom Boot Block Addresses.

Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and
any error conditions identified in the Status Register.The command set required to control the memory is consistent with JEDEC standards.

Erase can be suspended in order to perform either Read or Program in any other block and then resumed.Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles.

All blocks are protected during power-up. The M58BW032B features four different levels of hardware and software block protection to avoid unwanted program/erase operations:
Write/Protect Enable input, WP, provides a hardware protection of a combination of blocks from program or erase operations. The Block Protection configuration can be defined individually by issuing a Set Block Protection
Configuration Register or Clear Block Protection Configuration Register commands.
All Program or Erase operations are blocked when Reset,, is held low.
A Program/Erase Enable input, VPEN, is used to protect all blocks, preventing Program and Erase operations from affecting their data.
The Program and Erase commands can be

password protected by the Tuning Protection command.The M58BW032D offers the same protection features
with the exception of the Tuning Block Protection which is disabled in the factory.
A Reset/Power-down mode is entered when the RP input is Low. In this mode the power consumption is reduced to the standby level, the device is write protected and both the Status and Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High.

A manufacturer and device code are available.They can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory.

Finally, the M58BW032B/D features a Unique Device Identifier (UID) which is programmed by ST. It is unique for each die and can be used to implement cryptographic algorithms to improve security.

The memory is offered in PQFP80 (14 x 20mm) and LBGA80 (1.0mm pitch) packages and it is supplied with all the bits erased (set to '1').