M58CR064Q

The M58CR064 is a 64 Mbit (4Mbit x16) non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2V V_DD supply for the circuitry and a 1.65V to 3.3V V_DDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer
programming. In M58CR064C and M58CR064D the V_PP pin can also be used as a control pin to provide absolute protection against program or erase. In M58CR064P and M58CR064Q this feature is disabled.

The device features an asymmetrical block architecture.M58CR064 has an array of 135 blocks,and is divided into two banks, Banks A and B. The Dual Bank Architecture allows Dual Operations,while programming or erasing in one bank, Read operations are possible in the other bank. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory maps are shown in Figure 4. The Parameter Blocks are located at the top of the memory address space for the M58CR064C and M58CR064P, and at the bottom for the M58CR064D and M58CR064Q.

Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V_DD.

Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards.The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 54MHz.

The M58CR064 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. In M58CR064C and M58CR064D there is an additional hardware protection against program and erase. When V_PP  V_PPLK all blocks are protected against program or erase. All blocks are locked at Power- Up.

The device includes a Protection Register and a Security Block to increase the protection of a system's design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be
permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 5, shows the Security Block and Protection Register Memory Map.

The memory is offered in a TFBGA56, 6.5 x10mm, 0.75 mm ball pitch package and is supplied with all the bits erased (set to '1').