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Part Number: M5M4V16G50DFP-12

 

 

 

 

Description: The M5M4V16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM, with LVTTL interface. All inpu...


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M5M4V16G50DFP-12 General Description


The M5M4V16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V16G50DFP can operate at frequencies of 100+ MHz.The BLOCK WRITE and WRITE-PER-BIT functions provide improved performance in graphic memory systems.

M5M4V16G50DFP-12 Maximum Ratings

Symbol Parameter Conditions Ratings Unit
Vdd Supply Voltage with respect to Vss -0.5 ~ 4.6 V
VddQ Supply Voltage for Output with respect to VssQ -0.5 ~ 4.6 V
VI Input Voltage with respect to Vss -0.5 ~ 4.6 V
VO Output Voltage with respect to VssQ -0.5 ~ 4.6 V
IO Output Current   50 mA
Pd Power Dissipation Ta = 25 °C 1000 mW
Topr Operating Temperature   0 ~ 70 °C
Tstg Storage Temperature   -65 ~ 150 °C

M5M4V16G50DFP-12 Features

- Single 3.3v±0.3v power supply
- Clock frequencies of 125 MHz
- Fully synchronous operation referenced to clock rising edge
- Dual bank operation controlled by A10(Bank Address)
- Internal pipelined operation: column address can be changed every clock cycle
- Programmable /CAS Latency (LVTTL: 2 and 3)
- Programmable Burst Length (1/2/4/8 and Full Page)
- Programmable Burst Type (Sequential / Interleave)
- Byte control using DQM0 - DQM3 signals in both read and write cycles
- Persistent Write-Per-Bit (WPB) function
- 8 Column Block Write (BW) function
- Auto Precharge / All bank precharge controlled by A9
- Auto Refresh and Self Refresh Capability
- 2048 refresh cycles /32ms
- LVTTL Interface
- 100 pin QFP package with 0.65mm lead pitch

M5M4V16G50DFP-12 Connection Diagram

M5M4V16G50DFP-12  Connection Diagram

M5M4V16G50DFP-12 datasheet

M5M4V16G50DFP-12
PDF/DataSheet Download

  • Datasheet: M5M4V16G50DFP-12
  • File Size: 171571 KB
  • Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
  • Click here to Download

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