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Part Number: M5M4V64S40ATP-8
Description: The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit Synchronous DRAM, with LVTTL interface. All inpu...
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M5M4V64S40ATP-8
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General Description
M5M4V64S40ATP-8 General Description
The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S40ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.
M5M4V64S40ATP-8 Maximum Ratings
| Symbol | Parameter | Conditions | Ratings | Unit |
| Vdd | Supply Voltage | with respect to Vss | -0.5 ~ 4.6 | V |
| VddQ | Supply Voltage for Output | with respect to VssQ | -0.5 ~ 4.6 | V |
| VI | Input Voltage | with respect to Vss | -0.5 ~ Vdd+0.5 | V |
| VO | Output Voltage | with respect to VssQ | -0.5 ~ VddQ+0.5 | V |
| IO | Output Current | 50 | mA | |
| Pd | Power Dissipation | Ta = 25 °C | 1000 | mW |
| Topr | Operating Temperature | 0 ~ 70 | °C | |
| Tstg | Storage Temperature | -65 ~ 150 | °C |
M5M4V64S40ATP-8 Features
- Single 3.3v±0.3v power supply
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A7
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
- Clock frequency 125MHz /100MHz
- Auto precharge / All bank precharge controlled by A10
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A7
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
- Clock frequency 125MHz /100MHz
- Auto precharge / All bank precharge controlled by A10
M5M4V64S40ATP-8 Connection Diagram
M5M4V64S40ATP-8
PDF/DataSheet Download
- Datasheet: M5M4V64S40ATP-8
- File Size: 1110081 KB
- Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
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M5M4V64S40ATP-8 Relative Products
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The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S40ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory ...
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The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S30ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory o...
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The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S30ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory o...
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