Purchase M5M5T5636UG 25, In-stock M5M5T5636UG 25 From SeekIC.
Part Number: M5M5T5636UG 25
Description: The M5M5T5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is de...
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M5M5T5636UG 25
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DataSheet
General Description
M5M5T5636UG 25 General Description
The M5M5T5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5T5636UG operates on 2.5V power/ 1.8V I/O supply or a single 2.5V power supply and are 2.5V CMOS compatible.
M5M5T5636UG 25 Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
|
VDD |
Power Supply Voltage |
With respect to VSS |
-2.0*~3.6 |
V |
|
VDDQ |
I/O Buffer Power Supply Voltage |
-2.0*~3.6 |
V | |
|
VI |
Input Voltage |
-1.0~VDDQ+1.0* |
V | |
|
VO |
Output Voltage |
-1.0~VDDQ+1.0* |
V | |
|
PD |
Maximum Power Dissipation (VDD) |
1050 |
mW | |
|
TOPR |
Operating Temperature |
0~70 |
||
|
TSTG(bias) |
Storage Temperature(bias) |
-10~85 |
||
|
Tstg |
Storage Temperature |
-65~150 |
** This is 1.0V~VDDQ+1.0V when pulse width2ns, and 0.5V~VDDQ+0.5V in case of DC.
M5M5T5636UG 25 Features
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 250, 225, and 200 MHz
• Fast access time: 2.6, 2.8, 3.2 ns
• Single 2.5V -5% and +5% power supply VDD
• Separate VDDQ for 2.5V or 1.8V I/O
• Individual byte write (BWa# - BWd#) controls may be tied LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need to control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
• JTAG boundary scan support
• Fast clock speed: 250, 225, and 200 MHz
• Fast access time: 2.6, 2.8, 3.2 ns
• Single 2.5V -5% and +5% power supply VDD
• Separate VDDQ for 2.5V or 1.8V I/O
• Individual byte write (BWa# - BWd#) controls may be tied LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need to control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
• JTAG boundary scan support
M5M5T5636UG 25 Typical Application
High-end networking products that require high bandwidth, such as switches and routers.
M5M1
PDF/DataSheet Download
- Datasheet: M5M1
- File Size: 183622 KB
- Manufacturer: ETC [ETC]
- Click here to Download
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The M5M5T5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high p...
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