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M66222SP

Features: • Memory configuration of 128 × 8 bits × 2 memory areas• High-speed access, address access time 40ns (typ.)• Complete asynchronous accessibility from ports A and B• Fixed read/write access ports for memory• Completely static operation• Low power dissip...

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SeekIC No. : 004406866 Detail

M66222SP: Features: • Memory configuration of 128 × 8 bits × 2 memory areas• High-speed access, address access time 40ns (typ.)• Complete asynchronous accessibility from ports A and B•...

M66222SP Data Sheet

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Part Number:
M66222SP
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Description



Features:

• Memory configuration of 128 × 8 bits ×  2 memory areas
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Fixed read/write access ports for memory
• Completely static operation
• Low power dissipation CMOS design
• 5V single power supply
• TTL direct-coupled I/O
• 3-state output for I/O pins


Application

Inter-MCU data transfer memory, communication buffer memory


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Conditions
Rating
Unit
Vcc Supply voltage
 When defining GND pin as a
reference.
-0.3to+7.0
V
VI Input voltage
0.3 toVcc+0.3
V
Vo Output voltage
0 toVcc
V
Pd Maximum power dissipation Ta=25 °C
700
mW
Tstg Storage temperature  
-65 to +150
°C



Description

The M66222 is a mail box that incorporates two complete CMOS shared memory cells of 128×8-bit configuration using highperformance silicon gate CMOS process technology, and are equipped with two access ports of A and B.
Access ports A and B are equipped with independent addresses CS , WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations individually. This product exclusively performs a write operation from A port and a read operation from B port for one memory, and a read operation from A port and a write operation from B port for the other memory.




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