M672061E General Description
The M672061E implements a first-in first-out algorithm, eaturing asynchronous read/write operations. The FULL nd EMPTY flags prevent data overflow and underflow. he Expansion logic allows unlimited expansion in word ize and depth with no timing penalties. Twin address ointers automatically generate internal read and write ddresses, and no external address information are equired for the TEMIC FIFOs. Address pointers are utomatically incremented with the write pin and read in. The 9 bits wide data are used in data communications pplications where a parity bit for error checking is ecessary. The Retransmit pin reset the Read pointer to ero without affecting the write pointer. This is very seful for retransmitting data when an error is detected in he system.
Using an array of eight transistors (8 T) memory cell, the 672061E combine an extremely low standby supply urrent (typ = 0.1 A) with a fast access time at 15 ns ver the full temperature range. All versions offer battery ackup data retention capability with a typical power onsumption at less than 2 W.
For military/space applications that demand superior evels of performance and reliability the M672061E is rocessed according to the methods of the latest revision f the MIL STD 883 (class B or S) ,ESA SCC 9000 or ML.
M672061E Features
First-in first-out dual port memory
16384 * 9 organisation
Fast Flag and access times: 15, 30 ns
Wide temperature range : 55 °C to + 125 °C
Programmable Half Full Flag
Fully expandable by word width or depth
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation : 2 V data retention
TTL compatible
Single 5 V ± 10 % power supply
High Performance SCMOS Technology
M672061E Connection Diagram
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