Purchase MB90M405, In-stock MB90M405 From SeekIC.
- Table of contents:
MB90M405
-
Suppliers
DataSheet
General Description
MB90M405 Features
· Clock:
· PLL Clock multiplication circuit built-in
· Operating clock (PLL clock) generated by dividing original oscillation by 2 or by multiplying original oscillation by 1 to 4 (2.1 MHz to 16.8 MHz at original oscillation of 4.2 MHz). Can be selected.
· Minimum instruction execution time is 59.5 ns (when the original oscillation is 4.2 MHz, the PLL clock is generated by multiplying the original oscillation by 4, and Vcc = 3 V).
· It is possible to generate an external output as a clock output by dividing the original oscillation by 16, 32,64, or 128.
· Maximum memory space: 16 Mbytes
· 24-bit addressing in memory space
· Instruction system suited for controller
· Applicable data types (bit, byte, word, long-word)
· Various addressing modes: 23 types
· High code efficiency
· High-precision operation with 32-bit accumulator
· Signed multiplication and division instructions and enhanced RETI instruction
· Powerful instruction system applicable to high-level language (C) or multitasking
· System stack pointer
· Symmetric instruction set and barrel shift instruction
· Program patch function (2-address pointer)
· Shortened execution time: 4-byte instruction queue
· Powerful interrupt function (eight programmable priority levels)
· Powerful interrupt function for 32 interrupt factors
· Data transfer function (extended intelligent I/O service function: 16 channels maximum)
· Low-power consumption (standby mode)
· Sleep mode (stops CPU operating clock)
· Pseudo-timer mode (stops everything except original oscillation and time-base timer)
· Stop mode (stops original oscillation)
· CPU Intermittent operation mode
· Package
· QFP-100 (FPT-100P-M06: 0.65 mm pin pitch)
· Process
· CMOS technology
· PLL Clock multiplication circuit built-in
· Operating clock (PLL clock) generated by dividing original oscillation by 2 or by multiplying original oscillation by 1 to 4 (2.1 MHz to 16.8 MHz at original oscillation of 4.2 MHz). Can be selected.
· Minimum instruction execution time is 59.5 ns (when the original oscillation is 4.2 MHz, the PLL clock is generated by multiplying the original oscillation by 4, and Vcc = 3 V).
· It is possible to generate an external output as a clock output by dividing the original oscillation by 16, 32,64, or 128.
· Maximum memory space: 16 Mbytes
· 24-bit addressing in memory space
· Instruction system suited for controller
· Applicable data types (bit, byte, word, long-word)
· Various addressing modes: 23 types
· High code efficiency
· High-precision operation with 32-bit accumulator
· Signed multiplication and division instructions and enhanced RETI instruction
· Powerful instruction system applicable to high-level language (C) or multitasking
· System stack pointer
· Symmetric instruction set and barrel shift instruction
· Program patch function (2-address pointer)
· Shortened execution time: 4-byte instruction queue
· Powerful interrupt function (eight programmable priority levels)
· Powerful interrupt function for 32 interrupt factors
· Data transfer function (extended intelligent I/O service function: 16 channels maximum)
· Low-power consumption (standby mode)
· Sleep mode (stops CPU operating clock)
· Pseudo-timer mode (stops everything except original oscillation and time-base timer)
· Stop mode (stops original oscillation)
· CPU Intermittent operation mode
· Package
· QFP-100 (FPT-100P-M06: 0.65 mm pin pitch)
· Process
· CMOS technology
MB90M405 Connection Diagram
MB90M405
PDF/DataSheet Download
- Datasheet: MB90M405
- File Size: 218339 KB
- Manufacturer: FUJITSU [Fujitsu Media Devices Limited]
- Click here to Download
- ·MB90050
- FUJITSU [Fujitsu Media Devices Limited]
- On-Screen Display Controller
- 760910 KB
- ·MB90050PF
- FUJITSU [Fujitsu Media Devices Limited]
- On-Screen Display Controller
- 760910 KB
- ·MB90075
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCRREN DISPLAY CONTROLLER FOR NTSC/PAL
- 1988428 KB
- ·MB90075-PF
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCRREN DISPLAY CONTROLLER FOR NTSC/PAL
- 1988428 KB
- ·MB90075-P-SH
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCRREN DISPLAY CONTROLLER FOR NTSC/PAL
- 1988428 KB
- ·MB90089-PF
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCREEN DISPLAY CONTROLLER
- 2390199 KB
- ·MB90091
- FUJITSU [Fujitsu Media Devices Limited]
- Intelligent On-screen Display Controller (IOSDC)
- 416577 KB
- ·MB90091A
- FUJITSU [Fujitsu Media Devices Limited]
- Intelligent On-screen Display Controller (IOSDC)
- 416577 KB
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