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MB91101
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MFG:FUJ Package Cooled:QFP

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Part Number: MB91101

MFG: FUJ

Package Cooled: QFP

Description: The MB91101 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abu...

MB91101 General Description

The MB91101 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU, the MB91101 normally operates in the external bus access mode and executes instructions on the internal 1 Kbyte cache memory and 2 Kbytes RAM for enhanced performance.
The MB91101 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers.
*: FR Family stands for FUJITSU RISC controller.

MB91101 Maximum Ratings

Parameter		Symbol	Value		unit	Remarks
Parameter		Symbol	Min.	Max.	unit	Remarks
Power supply voltage	At 5 V power supply	V_CC5	V_SS 0.3	V_SS + 6.5	V
	At 5 V power supply	V_CC3	-	-	V
	At 3 V power supply	V_CC5	V_CC3 0.3	V_SS+ 6.5	V	*1
	At 3 V power supply	VC_C3	V_SS 0.3	V_SS+ 3.6	V	*1
Analog supply voltage		AV_CC	V_SS 0.3	V_SS + 3.6	V	*2
Analog reference voltage		AVRH	V_SS 0.3	V_SS+ 3.6	V	*2
Analog pin input voltage		V_IA	V_SS 0.3	AV_CC + 0.3	V
Input voltage		V_I	V_SS 0.3	V_CC5 + 0.3	V
Output voltage		V_O	V_SS 0.3	V_CC5+ 0.3	V
"L" level maximum output current		I_OL	-	10	mA	*3
"L" level average output current		I_OLAV	-	4	mA	*4
"L" level maximum total output current		I_OL	-	100	mA
"L" level average total output current		I_OLAV	-	50	mA	*5
"H" level maximum output current		I_OH	-	10	mA	*3
"H" level average output current		I_OHAV	-	4	mA	*4
"H" level maximum total output current		I_OH	-	50	mA
"H" level average total output current		I_OHAV	-	20	mA	*5
Power consumption		P_D	-	500	mW
Operating temperature		T_A	0	+70	°C
Storage temperature		Tstg	55	+150	°C

*1: V_CC5must not be less than V_SS 0.3 V.
*2: Make sure that the voltage does not exceed V_CC5+ 0.3 V, such as when turning on the device.
*3: Maximum output current is a peak current value measured at a corresponding pin.
*4: Average output current is an average current for a 100 ms period at a corresponding pin.
*5: Average total output current is an average current for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

MB91101 Features

FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
• General purpose registers: 32 bits ´ 16
• 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
• Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems
   supporting high level languages
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots: Reduced overhead time in branch executions
• Internal multiplier/supported at instruction level
   Signed 32-bit multiplication: 5 cycles
   Signed 16-bit multiplication: 3 cycles
• Interrupt (push PC and PS): 6 cycles, 16 priority levels
External bus interface
• Clock doubler: Internal 50 MHz, external bus 25 MHz operation
• 25-bit address bus (32 Mbytes memory space)
• 8/16-bit data bus
• Basic external bus cycle: 2 clock cycles
• Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6
• Interface supported for various memory technologies
    DRAM interface (area 4 and 5)
• Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
• Unused data/address pins can be configured us input/output ports
• Little endian mode supported (Select 1 area from area 1 to 5)
DRAM interface
• 2 banks independent control (area 4 and 5)
• Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM
• Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
• Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
• DRAM refresh
CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode
• Supports 8/9/10/12-bit column address width
• 2CAS/1WE, 2WE/1CAS selective
Cache memory
• 1-Kbyte instruction cache memory
• 32 block/way, 4 entry(4 word)/block
• 2 way set associative
• Lock function: For specific program code to be resident in cashe memory
DMA controller (DMAC)
• 8 channels
• Transfer incident/external pins/internal resource interrupt requests
• Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
• Transfer data length: 8 bits/16 bits/32 bits selective
• NMI/interrupt request enables temporary stop operation
UART
• 3 independent channels
• Full-duplex double buffer
• Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
• Asynchronous (start-stop system), CLK-synchronized communication selective
• Multi-processor mode
• Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate
• Use external clock can be used as a transfer clock
• Error detection: Parity, frame, overrun
10-bit A/D converter (successive approximation conversion type)
• 10-bit resolution, 4 channels
• Successive approximation type: Conversion time of 5.6 ms at 25 MHz
• Internal sample and hold circuit
• Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective
• Start: Software/external trigger/internal timer selective
16-bit reload timer
• 3 channels
• Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective
Other interval timers
• 16-bit timer: 3 channels (U-TIMER)
• PWM timer: 4 channels
• Watchdog timer: 1 channel
Bit search module
First bit transition "1" or "0" from MSB can be detected in 1 cycle
Interrupt controller
• External interrupt input: Non-maskable interrupt (NMI), normal interrupt ´ 4 (INT0 to INT3)
• Internal interrupt incident:UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt
                                             module
• Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps)
Others
• Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset
• Low-power consumption mode: Sleep mode/stop mode
• Clock control
   Gear function: Operating clocks for CPU and peripherals are independently selective
                          Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16)
                          However, operating frequency for peripherals is less than 25 MHz.
• Packages: LQFP-100 and QFP-100
• CMOS technology (0.35 mm)
• Power supply voltage
   5 V: CPU power supply 5.0 V ±10% (internal regulator)
         A/D power supply 2.7 V to 3.6 V
   3 V: CPU power supply 2.7 V to 3.6 V (without internal regulator)
         A/D power supply 2.7 V to 3.6 V

MB91101 Connection Diagram

MB91101 datasheet

MB91101
PDF/DataSheet Download

Datasheet: MB91101
File Size: 1263514 KB
Manufacturer: FUJITSU [Fujitsu Media Devices Limited]
Click here to Download

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