Features: • FR60 CPU• 32-bit RISC, load/store architecture, five-stage pipeline• Operating frequency of 80 MHz (PLL clock multiplied)• 16-bit fixed-length instructions (basic instructions)• Instruction execution speed : one instruction per cycle• Memory-to-memor...
MB91470: Features: • FR60 CPU• 32-bit RISC, load/store architecture, five-stage pipeline• Operating frequency of 80 MHz (PLL clock multiplied)• 16-bit fixed-length instructions (basic...
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| Parameter | Symbol | Rating | Unit | Remarks | |
| Min | Max | ||||
| Power supply voltage*1 | VCC | VSS − 0.5 | VSS + 6.0 | V | |
| Analog power supply voltage*1,*2,*6 |
AVCC10 AVCC12 |
VSS − 0.5 | VSS + 6.0 | V | |
| Analog reference voltage*7 | AVRHn | VSS − 0.5 | VSS + 6.0 | V | |
| Input voltage*1 | VI | VSS − 0.3 | VCC + 0.3 | V | |
| Analog pin input voltage*1 | VIA | VSS − 0.3 | AVCC + 0.3 | V | |
| Output voltage*1 | VO | VSS − 0.3 | VCC + 0.3 | V | |
| "L" level maximum output current*3 |
IOL | - | 10 | mA | |
| "L" level average output current*4 |
IOLAV | - | 4 | mA | Except port Q0 to Q5 and S0 to S5 |
| 12 | mA | Port Q0 to Q5 and S0 to S5 | |||
| "L" level total maximum output current |
IOL | - | 100 | mA | |
| "L" level total average output current*5 |
IOLAV | - | 50 | mA | |
| "H" level maximum output current*3 |
IOH | - | -10 | mA | |
| "H" level average output current *4 |
IOHAV | - | -4 | mA | Except port Q0 to Q5 and S0 to S5 |
| -12 | mA | Port Q0 to Q5 and S0 to S5 | |||
| "H" level total maximum output current |
IOH | - | -100 | mA | |
| "H" level total average output current*5 |
IOHAV | - | -50 | mA | |
| Power consumption | PD | - | 800 | mW | |
| Storage temperature | TSTG | −55 | +125 | °C | |