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Part Number: MB91F133
Description: The MB91133/MB91F133, a standard single-chip microcontroller featuring various I/O resources and bus controlmechani...
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MB91F133
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DataSheet
General Description
MB91F133 General Description
The MB91133/MB91F133, a standard single-chip microcontroller featuring various I/O resources and bus control
mechanisms to incorporate the control required for high-performance high-speed CPU processes, is the core unit
in the 32-bit RISC CPU (FR family) .
This unit has the optimal specifications for incorporating applications that require high-performance CPU pro-cessing power by featuring peripheral I/O resources suitable for single-lens reflex cameras, digital video cameras,etc.
MB91F133 Maximum Ratings
*1 : Care must be taken that this does not exceed VCC5 + 0.3 V when the power is turned on. Also, care must be
taken that AVCC does not exceed VCC5 when the power is turned on. AVCC should be set at the same electrical
potential as VCC5.
*2 : Peak value of the pin concerned is regulated as the maximum output current.
*3 : Average current within 100 ms flowing in the pin concerned is regulated as the average output current.
*4 : Average current within 100 ms flowing in all pins concerned is regulated as the average total output current.
MB91F133 Features
CPU
• 32-bit RISC (FR30) , load/store architecture, 5-level pipeline
• Multi-purpose register : 32 bits * 16
• 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle
• Instructions for barrel shift, bit processing and inter-memory transfers : Instructions suited to loading purposes
• Function entry / exit instruction, multi load / store instruction of register details : High-level language handling
instruction
• Register interlock function : Simplification of assembler description
• Branch instruction with delay slot : Reduction in overheads in case of branching
• Multiplier is built-in / supported at instruction level.
• Signed 32-bit multiplication : 5 cycles
• Signed 16-bit multiplication : 3 cycles
• Interruption (saving PC and PS) : 6 cycles, 16 priority levels
2. Bus Interface
• 24-bit address output, 8/16-bit data input/output
• Basic bus cycle : 2 clock cycles
• Interface support for various memories
• Unused data and address pins can be used as input/output ports.
• Supports "little endian" mode
3. Built-in ROM
Mask device : 254 KB; FLASH device : 254 KB; EVA-FLASH device : 254 KB
4. Built-in RAM
Mask device : 8 KB; FLASH device : 8 KB; EVA-FLASH device : 8 KB
5. DMA Controller
This is a descriptor-type MA controller whose transfer parameters are arranged in the main memory.
A maximum of 8 factors in total (internal and external) can be transferred.
External factors are 3 channels.
6. Bit Search Module
Searches the first "1" / "0" change bit positions within 1 cycle from MSB in 1 word
7. Timer
• 16-bit reload timer * 5 channels
• 16-bit OCU * 8 channels, ICU * 4 channels, free-run timer * 1 channel
Output waveform adjusting function for AC motor waveforms is included in the above timer.
• 8/16-bit up/down timer/counter (8-bit * 2 channels or 16-bit * 1 channel)
External interruption and pin are shared for AIN and BIN.
• 16-bit down count timer * 5 channels; can also be used as the UART baud rate timer
• 16-bit PPG timer * 6 channels; out-pulse cycle / duty can be changed at random
8. D/A Converter
•8-bit * 3 channels
9. A/D Converter (Sequential comparison type)
• 10-bit * 8 channels
• Sequential conversion method (conversion time 5.0 µs at 33 MHz)
• Setting for single conversion, scan conversion and repeat conversion is possible.
• Conversion starting function using hardware or software
10. Serial I/O
•UART * 5 channels; clock synchronous serial transfer with LSB / MSB switching function is possible for both.
• Serial data output or serial lock output can be selected using push-pull / open-drain software.
11. Level Comparator Input
• 1 channel; shared input and pins of A/D converter.
12. Clock Switching Function
• Base clock : Software can be used to select from two types of clock sources, namely 32 kHz and high-speed.
• Gear function : Four types of settings (1 : 1, 1 : 2, 1 : 4, 1 : 8) can be set individually as the operating clock
ratio to the basic clock per CPU and peripheral equipment.
13. Interruption Controller
• External interruption input (total 24 channels)
• With pull up pin control / standby return function : 4 channels
(rising / falling / H level / L level settings are possible)
• With pull up pin control / standby return function; AIN / BIN pins of the up/down counter are shared : 4 channels
(rising / falling / H level / L level settings are possible)
• With pull up pin controln : 16 channels
(rising / falling / H level / L level settings are possible)
• Internal interruption factor
• Interruption / delay interruption by resource
14. Others
• Reset factors
Power on reset, watchdog timer, software reset, external reset
• Low power consumption mode
Sleep/stop mode
• Packages
FBGA-144, LQFP-144
• CMOS technology (0.35 µm)
• Power
Two power sources (5 V / 3 V)
1) 5 V system : 5 V ± 10% (A/D, D/A and level comparator included)
2) 3 V system : A) 3.0 V to 3.6 V : All functions guaranteed
B) 2.7 V to 3.0 V : All functions guaranteed for single-chip mode of mask devices only
• 32-bit RISC (FR30) , load/store architecture, 5-level pipeline
• Multi-purpose register : 32 bits * 16
• 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle
• Instructions for barrel shift, bit processing and inter-memory transfers : Instructions suited to loading purposes
• Function entry / exit instruction, multi load / store instruction of register details : High-level language handling
instruction
• Register interlock function : Simplification of assembler description
• Branch instruction with delay slot : Reduction in overheads in case of branching
• Multiplier is built-in / supported at instruction level.
• Signed 32-bit multiplication : 5 cycles
• Signed 16-bit multiplication : 3 cycles
• Interruption (saving PC and PS) : 6 cycles, 16 priority levels
2. Bus Interface
• 24-bit address output, 8/16-bit data input/output
• Basic bus cycle : 2 clock cycles
• Interface support for various memories
• Unused data and address pins can be used as input/output ports.
• Supports "little endian" mode
3. Built-in ROM
Mask device : 254 KB; FLASH device : 254 KB; EVA-FLASH device : 254 KB
4. Built-in RAM
Mask device : 8 KB; FLASH device : 8 KB; EVA-FLASH device : 8 KB
5. DMA Controller
This is a descriptor-type MA controller whose transfer parameters are arranged in the main memory.
A maximum of 8 factors in total (internal and external) can be transferred.
External factors are 3 channels.
6. Bit Search Module
Searches the first "1" / "0" change bit positions within 1 cycle from MSB in 1 word
7. Timer
• 16-bit reload timer * 5 channels
• 16-bit OCU * 8 channels, ICU * 4 channels, free-run timer * 1 channel
Output waveform adjusting function for AC motor waveforms is included in the above timer.
• 8/16-bit up/down timer/counter (8-bit * 2 channels or 16-bit * 1 channel)
External interruption and pin are shared for AIN and BIN.
• 16-bit down count timer * 5 channels; can also be used as the UART baud rate timer
• 16-bit PPG timer * 6 channels; out-pulse cycle / duty can be changed at random
8. D/A Converter
•8-bit * 3 channels
9. A/D Converter (Sequential comparison type)
• 10-bit * 8 channels
• Sequential conversion method (conversion time 5.0 µs at 33 MHz)
• Setting for single conversion, scan conversion and repeat conversion is possible.
• Conversion starting function using hardware or software
10. Serial I/O
•UART * 5 channels; clock synchronous serial transfer with LSB / MSB switching function is possible for both.
• Serial data output or serial lock output can be selected using push-pull / open-drain software.
11. Level Comparator Input
• 1 channel; shared input and pins of A/D converter.
12. Clock Switching Function
• Base clock : Software can be used to select from two types of clock sources, namely 32 kHz and high-speed.
• Gear function : Four types of settings (1 : 1, 1 : 2, 1 : 4, 1 : 8) can be set individually as the operating clock
ratio to the basic clock per CPU and peripheral equipment.
13. Interruption Controller
• External interruption input (total 24 channels)
• With pull up pin control / standby return function : 4 channels
(rising / falling / H level / L level settings are possible)
• With pull up pin control / standby return function; AIN / BIN pins of the up/down counter are shared : 4 channels
(rising / falling / H level / L level settings are possible)
• With pull up pin controln : 16 channels
(rising / falling / H level / L level settings are possible)
• Internal interruption factor
• Interruption / delay interruption by resource
14. Others
• Reset factors
Power on reset, watchdog timer, software reset, external reset
• Low power consumption mode
Sleep/stop mode
• Packages
FBGA-144, LQFP-144
• CMOS technology (0.35 µm)
• Power
Two power sources (5 V / 3 V)
1) 5 V system : 5 V ± 10% (A/D, D/A and level comparator included)
2) 3 V system : A) 3.0 V to 3.6 V : All functions guaranteed
B) 2.7 V to 3.0 V : All functions guaranteed for single-chip mode of mask devices only
MB91F133 Connection Diagram
MB91F133A
PDF/DataSheet Download
- Datasheet: MB91F133A
- File Size: 1145542 KB
- Manufacturer: Fujitsu
- Click here to Download
- ·MB90050
- FUJITSU [Fujitsu Media Devices Limited]
- On-Screen Display Controller
- 760910 KB
- ·MB90050PF
- FUJITSU [Fujitsu Media Devices Limited]
- On-Screen Display Controller
- 760910 KB
- ·MB90075
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCRREN DISPLAY CONTROLLER FOR NTSC/PAL
- 1988428 KB
- ·MB90075-PF
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCRREN DISPLAY CONTROLLER FOR NTSC/PAL
- 1988428 KB
- ·MB90075-P-SH
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCRREN DISPLAY CONTROLLER FOR NTSC/PAL
- 1988428 KB
- ·MB90089-PF
- FUJITSU [Fujitsu Media Devices Limited]
- ON-SCREEN DISPLAY CONTROLLER
- 2390199 KB
- ·MB90091
- FUJITSU [Fujitsu Media Devices Limited]
- Intelligent On-screen Display Controller (IOSDC)
- 416577 KB
- ·MB90091A
- FUJITSU [Fujitsu Media Devices Limited]
- Intelligent On-screen Display Controller (IOSDC)
- 416577 KB
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