MC100E171

MC100E167FN

The MC100E167FN contains six 2:1 multiplexers followed by Dflip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HI...

MC100E167

MC100E166

MC100E164

The MC100E164 is a 16:1 multiplexer with a differential output. The select inputs (SEL0, 1, 2, 3 ) control which one of the sixteen data inputs (A0 A15) is propagated to the output.Special attention to the design layout results in a typical skew between the...

MC100E163

The MC100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs (SEL0, 1, 2) control which one of the eight data inputs (A0 A7, B0 B7) is propagated to the output

MC100E160

The MC100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN ) forces the Q output LOW.The MC100E160 also features an output register. Multiplexers direct the register input, g...