MC68B50CP

The MC68B50CP asynchronous communications interface adapter provides the data formatting and control to interface serial asynchronous data communications information to bus organized systems such as the MC68B50CP microprocessing unit.

The bus interface of the MC68B50CP includes select,enable,read/write,interrupt and bus interface logic to allow data transfer over an 8-bit bidirectional data bus.The parallel data of the bus system is serially transmitted and received by the asynchronous data interface,with proper formatting and error checking.The functional configuration of the ACIA is programmable control register provides variable word lengths,clock division ratios,transmit control,receive control lines are provided.These lines allow the ACLA to interface directly with the MC6860L 0-600 bps digital modem.

The MC68B50CP has ten features.(1)8- and 9-bit transmission.(2)optional even and odd parity.(3)parity,overrun and framing error checking.(4)programmable control register.(5)optional /1,/16,and /64 clock modes.(6)up to 1.0 Mbps transmission.(7)false start bit deletion.(8)peripheral/modem control functions.(9)double buffered.(10)one-or two-stop bit operation.