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Part Number: MC68HC705P6A

 

 

Package Cooled: FREESCALE

D/C: 07+

Description: The following paragraphs describe the functionality of each pin on the MC68HC705P6A package. Pins connected to subsyste...


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MC68HC705P6A General Description


The following paragraphs describe the functionality of each pin on the MC68HC705P6A package. Pins connected to subsystems described in other chapters provide a reference to the chapter instead of a detailed functional description.

MC68HC705P6A Features

•Low cost
•M68HC05 core
•28-pin SOIC, PDIP, or windowed DIP package
•4672 bytes of user EPROM (including 48 bytes of page zero
 EPROM and 16 bytes of user vectors)
•239 bytes of bootloader ROM
•176 bytes of on-chip RAM
•4-channel 8-bit A/D converter
•SIOP serial communications port
•16-bit timer with output compare and input capture
•20 bidirectional I/O lines and 1 input-only line
•PC0 and PC1 high-current outputs
•Single-chip, bootloader, and test modes
•Power-saving stop, halt, and wait modes
•Static EPROM mask option register (MOR) selectable options:
COP watchdog timer enable or disable
Edge-sensitive or edge- and level-sensitive external interrupt
SIOP most significant bit (MSB) or least significant bit (LSB) first
SIOP clock rates: OSC divided by 8, 16, 32, or 64
Stop instruction mode, STOP or HALT
EPROM security external lockout
Programmable keyscan (pullups/interrupts) on PA0PA7

MC68HC705P6A Connection Diagram

MC68HC705P6A Connection Diagram

MC68HC705P6A datasheet

MC68HC705P6A
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