MCM67T415 Features
• 16K x 15 Configuration:
12 Tag Bits
Three Status Bits (Valid, Dirty, and WT)
• Valid Bit used to Qualify Match Output
• HighSpeed AddresstoMatch Comparison Times 9/10/12 ns
• BRDY Circuitry Included Inside the CacheTag for the Highest Speed Operation
• Asynchronous Read/Match Operation and Synchronous Write and Reset Operation
• Separate Write Enable for Tag Bits and Status Bits
• Separate Output Enable for Tag Bits, Status Bits, andBRDY
• Synchronous RESET Pin for Invalidation of all Tag Entries
• Dual Chip Selects for Easy Depth Expansion with No Performance Degradation
• I/O Pins Both 5 V TTL and 3.3 V LVTTL Compatible with VCCQ Pins
• PWRDN Pin to Place Device in LowPower Mode
• DropIn Replacement for IDT71215
• Packaged in an 80Pin Thin Quad Flat Pack (TQFP)
MCM67T415 Connection Diagram
Map list: ABCDEFGHIJKLMNOPQRSTUVWXYZ 0123456789All