MK50H27

The SGS - Thomson SS7 Signalling Link Controller (MK50H27) is a VLSI semiconductor device which provides a complete level 2 data communication control conforming to the CCITT, ANSI,  BELLCORE, and AT&T versions of SS7, as well as options to allow conformance to TTC JT-Q703 (Japanese SS7). This includes signal unit formatting, transparency (so-called "bit-stuffing"), error recovery by two types of retransmission, error monitoring, sequence number control, link status control, and fill in signal unit generation.

One of the outstanding features of the MK50H27 is its buffer management which includes on-chip DMA. This feature allows users to handle multiple MSU's of receive and transmit data at a time. (A conventional data link control chip plus a separate DMA chip would handle data for only a single block at a time.) The MK50H27 will move multiple blocks of receive and transmit data directly into and out of memory through the Host's bus. A possible system configuration for the MK50H27 is shown in figure 1.

For added flexibility a transparent mode provides an HDLC transport mechanism without link layer support. In this mode no protocol processing is done, all data received between opening flag and CRC is written to the shared memory buffer and it is up to the user to take care of the upper level software.

The MK50H27 may be used with any of several popular microprocessors, such as: 68040 ... 68000, 6800, Z8000, Z80, 80486 ... 8086, i960, etc.

The MK50H27 may be operated in either full or half duplex mode. In half duplex mode, the RTS and CTS modem control pins are provided. In full duplex mode, these pins become user programmable I/O pins. All signal pins on the MK50H27 are TTL compatible. This has the advantage of making the MK50H27 independent of the physical interface. As shown in figure 1, line drivers and receivers are used for electrical connection to the physical layer.