Features: • Total number of pixels: 798 (horizontal) × 584 (vertical)• High sensitivity• Broad dynamic range(compared to our conventional CCD ×1.2)• Low smear• Electronic shutter• No image distortion• Small size enables design of compact equipment• H...
MN39243FT: Features: • Total number of pixels: 798 (horizontal) × 584 (vertical)• High sensitivity• Broad dynamic range(compared to our conventional CCD ×1.2)• Low smear• Electron...
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|
Parameter |
Symbol |
Rating |
Unit | ||
|
min |
max |
V | |||
| Reset drain voltage |
VRD |
-0.2 |
18.0 | ||
| Output drain voltage |
VOD |
-0.2 |
18.0 | ||
| Output load transistor gate voltage |
VLG |
(Internal bias) | |||
| Output gate voltage |
VOG |
(Internal bias) | |||
| Horizontal CCD input source voltage |
VIS |
-0.2 |
18.0 | ||
| Protection P-well voltage |
VPT *3, 4 |
-9.0 |
0.2 | ||
| P-well voltage |
VPW |
Reference voltage | |||
| Reset pulse voltage |
High-Low |
VR(H-L)*1 |
- |
5.0 | |
| Bias |
VR(Bias)*1 |
-0.2 |
- | ||
| Horizontal register clock pulse voltage 1 |
VH1(H) |
- |
5.0 | ||
|
VH1(L) |
-0.2 |
- | |||
| Horizontal register clock pulse voltage 2 |
VH2(H) |
- |
5.0 | ||
|
VH2(L) |
-0.2 |
- | |||
| Vertical shift register clock pulse voltage 1 |
VV1(H)*3,4 |
- |
18.0 | ||
|
VV1(M)*3,4 |
- |
- | |||
|
VV1(L)*3,4 |
-9.0 |
- | |||
| Vertical shift register clock pulse voltage 2 |
VV2(M)*3,4 |
- |
15.0 | ||
|
VV2(L)*3,4 |
-9.0 |
- | |||
| Vertical shift register clock pulse voltage 3 |
VV3(H)*3,4 |
- |
18.0 | ||
|
VV3(M)*3,4 |
- |
- | |||
|
VV3(L)*3,4 |
-9.0 |
- | |||
| Vertical shift register clock pulse voltage 4 |
VV4(M)*3,4 |
- |
15.0 | ||
|
VV4(L)*3,4 |
-9.0 |
- | |||
| Substrate voltage |
VSub*2 |
-0.2 |
45.0 | ||
|
VSub*2 | |||||
| Operating temperature |
Topr |
-10 |
70 |
°C | |
| Storage temperature |
Tstg |
-30 |
80 |
°C | |