MPC857DSL Selling Leads, Price trend, MPC857DSL DataSheet download, circuit diagram from SeekIC.com

Features: The following list summarizes the key MPC862/857T/857DSL features:• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs)- The core performs branch prediction with conditional prefetch, without cond...

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Features:

The following list summarizes the key MPC862/857T/857DSL features:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs)
- The core performs branch prediction with conditional prefetch, without conditional execution
- 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1-1).
16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks.
Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis.
- MMUs with 32-entry TLB, fully associative instruction and data TLBs
- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups
- Advanced on-chip-emulation debug mode
• The MPC862/857T/857DSL provides enhanced ATM functionality over that of the MPC860SAR. The MPC862/857T/857DSL adds major new features available in "enhanced SAR" (ESAR) mode, including the following:
- Improved operation, administration and maintenance (OAM) support
- OAM performance monitoring (PM) support
- Multiple APC priority levels available to support a range of traffic pace requirements
- ATM port-to-port switching capability without the need for RAM-based microcode
- Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability
- Optional statistical cell counters per PHY
- UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell transmission time. (The earlier UTOPIA level 1 specification is also supported.)
Multi-PHY support on the MPC857T
Four PHY support on the MPC857DSL
- Parameter RAM for both SPI and I2
C can be relocated without RAM-based microcode
- Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a "split" bus
- AAL2/VBR functionality is ROM-resident
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Memory controller (eight banks)
- Contains complete dynamic RAM (DRAM) controller
- Each bank can be a chip select or RAS to support a DRAM bank
- Up to 30 wait states programmable per memory bank
- Glueless interface to Page mode/EDO/SDRAM, SRAM, EPROMs, flash EPROMs, and other memory devices.
- DRAM controller programmable to support most size and speed memory interfaces
- Four CAS lines, four WE lines, one OE line
- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
- Variable block sizes (32 Kbyte256 Mbyte)
- Selectable write protection
- On-chip bus arbitration logic
• General-purpose timers
- Four 16-bit timers cascadable to be two 32-bit timers
- Gate mode can enable/disable counting
- Interrupt can be masked on reference match and event capture
• Fast Ethernet controller (FEC)
- Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA multiplexed bus.
• System integration unit (SIU)
- Bus monitor
- Software watchdog
- Periodic interrupt timer (PIT)
- Low-power stop mode
- Clock synthesizer
- Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
- Reset controller
- IEEE 1149.1 test access port (JTAG)
• Interrupts
- Seven external interrupt request (IRQ) lines
- 12 port pins with interrupt capability
- The MPC862P and MPC862T have 23 internal interrupt sources; the MPC857T and MPC857DSL have 20 internal interrupt sources
- Programmable priority between SCCs (MPC862P and MPC862T)
- Programmable highest priority request
• Communications processor module (CPM)
- RISC controller
- Communication-specific commands (for example, GRACEFULSTOPTRANSMIT,ENTERHUNTMODE, andRESTART TRANSMIT)
- Supports continuous mode transmission and reception on all serial channels
- Up to 8-Kbytes of dual-port RAM
- The MPC862P and MPC862T have 16 serial DMA (SDMA) channels; the MPC857T and MPC857DSL have 10 serial DMA (SDMA) channels
- Three parallel I/O registers with open-drain capability
• Four baud rate generators
- Independent (can be connected to any SCC or SMC)
- Allow changes during operation
- Autobaud support option
• The MPC862P and MPC862T have four SCCs (serial communication controller) The MPC857T and MPC857DSL have one SCC, SCC1; the MPC857DSL supports ethernet only
- Serial ATM capability on all SCCs
- Optional UTOPIA port on SCC4
- Ethernet/IEEE 802.3 optional on SCC14, supporting full 10-Mbps operation
- HDLC/SDLC
- HDLC bus (implements an HDLC-based local area network (LAN))
- Asynchronous HDLC to support PPP (point-to-point protocol)
- AppleTalk
- Universal asynchronous receiver transmitter (UART)
- Synchronous UART
- Serial infrared (IrDA)
- Binary synchronous communication (BISYNC)
- Totally transparent (bit streams)
- Totally transparent (frame based with optional cyclic redundancy check (CRC))
• Two SMCs (serial management channels) (The MPC857DSL has one SMC, SMC1 for UART)
- UART
- Transparent
- General circuit interface (GCI) controller
- Can be connected to the time-division multiplexed (TDM) channels
• One serial peripheral interface (SPI)
- Supports master and slave modes
- Supports multiple-master operation on the same bus
• One inter-integrated circuit (I²C) port
- Supports master and slave modes
- Multiple-master environment support
• Time-slot assigner (TSA) (The MPC857DSL does not have the TSA)
- Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
- Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
- 1- or 8-bit resolution
- Allows independent transmit and receive routing, frame synchronization, clocking
- Allows dynamic changes
- On the MPC862P and MPC862T, can be internally connected to six serial channels (four SCCs and two SMCs); on the MPC857T, can be connected to three serial channels (one SCC and two SMCs)
• Parallel interface port (PIP)
- Centronics interface support
- Supports fast connection between compatible ports on MPC862/857T/857DSL or MC68360
• PCMCIA interface
- Master (socket) interface, release 2.1 compliant
- Supports one or two PCMCIA sockets dependant upon whether ESAR functionality is enabled
- 8 memory or I/O windows supported
• Low power support
- Full on-All units fully powered
- Doze-Core functional units disabled except time base decrementer, PLL, memory controller, RTC, and CPM in low-power standby
- Sleep-All units disabled except RTC, PIT, time base, and decrementer with PLL active for fast wake up
- Deep sleep-All units disabled including PLL except RTC, PIT, time base, and decrementer.
- Power down mode- All units powered down except PLL, RTC, PIT, time base and decrementer
• Debug interface
- Eight comparators: four operate on instruction address, two operate on data address, and two operate on data
- Supports conditions: =< >
- Each watchpoint can generate a break point internally
• 3.3 V operation with 5-V TTL compatibility except EXTAL and EXTCLK
• 357-pin plastic ball grid array (PBGA) package
• Operation up to 100MHz

Specifications

Rating	Symbol	Value	Unit	Max Freq (MHz)
Supply voltage¹	VDDH	-0.3 to 4.0	V	-
	VDDL	-0.3 to 4.0	V	-
	KAPWR	-0.3 to 4.0	V	-
	VDDSYN	-0.3 to 4.0	V	-
Input voltage²	V_in	GND-0.3 to VDDH	V	-
Temperature3(standard)⁴	T_A(min)	0	˚C	100
Temperature3(standard)⁴	T_j(max)	105	˚C	100
Temperature3(extended)	T_A(min)	-40	˚C	80
Temperature3(extended)	T_j(max)	115	˚C	80
Storage temperature range	T_stg	-55 to +150	˚C	-

1The power supply of the device must start its ramp from 0.0 V.
2Functional operating conditions are provided with the DC electrical specifications in Table 6-5. Absolute
maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond
those listed may affect device reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction
applies to power-up and normal operation (that is, if the MPC862/857T/857DSL is unpowered, voltage greater
than 2.5 V must not be applied to its inputs).
3Minimum temperatures are guaranteed as ambient temperature, T_A. Maximum temperatures are guaranteed asjunction temperature, T_j.
4JTAG is tested only at ambient, not at standard maximum or extended maximum

MPC857DSL

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