MX29VW160T

The MX29VW160T/B is a 16Mbit Flash memory organized as either 2M-byte by 8-bit or 1M-word by 16-bit. To provide simultaneous operation which can read a data while program/erase,the 16Mbits of data is divided into two banks of bank A ( 2M bit) and bank B(14M bit). Bank A is organized by eight 8K-byte blocks and three 64k-byte blocks. Bank B is organized by twenty-eight 64K-byte blocks.

To allow for simple in-system operation with very low operation voltage, MX29VW160T/B can be operated with a single 2.25V to 3.0V supply voltage.Manufactured with MXIC's advanced nonvolatile memory technology, the device offers access times of 120ns, and a low 1uA typical standby current.

The MX29VW160T/B command set is compatible with the JEDEC single-power-supply flash standard.Commands are written to the command register using standard micro-processor write timings. MXIC's flash memory augments EPROM functionality with an internal state machine which controls the erase and program circuitry. The device RY/BY pin provides a convenient way to monitor when a program or erase cycle is complete.

Programming the MX29VW160T/B is performed on a page basis; 128 bytes of data are loaded into the device and then programmed simultaneously. The typical Page Program time is 4ms. The device can also be reprogrammed in standard EPROM programmers.Reading data out of the device is similar to reading from an EPROM or other flash.

Erase is accomplished by executing the Erase command sequence. This will invoke the Auto Erase algorithm which is an internal algorithm that automatically times the erase pulse widths and verifies proper cell margin.This device features both chip erase and block erase.Each block can be erased and programmed without affecting other blocks. Using MXIC's advance design technology, no preprogram is required (internally or externally). As a result, the whole chip can be typically erased and verified in as fast as 50ms.

A combined feature of Reset Pin (RP), a hardware lockout bit, and software command sequences provide complete data protection. First, software data protection protects the device from inadvertent program or erase. Two "unlock" write cycles must be presented to the device before the program or erase command can be accepted by the device. For hardware data protection,the RP pin provide protection against unwanted command writes due to invalid system bus condition that may occur during system reset and power up/down sequence.Finally, with a hardware lockout bit feature, the device provides complete core security for the kernal code required for system initialization.

MXIC's flash technology reliably stores memory contents after 100,000 erase and program cycles. The MXIC's cell is designed to optimize the erase and program mechanism. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produce reliable cycling.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to Vcc+1V.