MFG:FAICHILD Package Cooled:TO-220 D/C:08+
MFG: FAICHILD
Package Cooled: TO-220
D/C: 08+
Description: These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprie...
These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
|
Symbol |
Parameter |
NDP4050 |
NDB4050 |
Units |
|
VDSS |
Drain-Source Voltage |
60 |
V | |
|
VDGR |
Drain-Gate Voltage (RGS 1 MW) |
60 |
V | |
|
VGSS |
Gate-Source Voltage - Continuous - Nonrepetitive (tP < 50 µs) |
± 20 |
V | |
|
± 40 | ||||
|
ID |
Drain Current - Continuous - Pulsed |
± 15 |
A | |
|
± 45 | ||||
|
PD |
Total Power Dissipation Derate above 25°C |
50 |
W | |
|
0.33 |
W/ | |||
|
TJ,TSTG |
Operating and Storage Temperature Range |
-65 to 175 |
||
|
TL |
Maximum lead temperature for soldering purposes,1/8" from case for 5 seconds |
275 |
||
NDP4060
PDF/DataSheet Download
These logic level N-Channel enhancement mode power field effect transistors NDP4050L are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, ...
These N-Channel enhancement mode power field effect transistors NDP4050are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superi...
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