PLL102-15

·  Frequency range 25 ~ 60MHz. 
·  Internal phase locked loop will allow spread spec-trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation).
·  Zero input - output delay. 
·  Less than 700 ps device - device skew.
·  Less than 250 ps skew between outputs.
·  Less than 200 ps cycle - cycle jitter.
·  Output Enable function tri -state outputs.
·  3.3V operation.
·  Available in 8 -Pin 150mil SOIC.

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability.  These conditions represent a stress rating only, and functional operations of the device at these or any other con-ditions above the operational limits noted in this specification is not implied. 

The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to di stribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. PLL102-15 has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to the input of the PLL. Since the skew b etween the input and output is less than ±350 ps, the device acts as a zero delay buffer.