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Part Number: PLL103-02

 

 

 

 

Description: The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. Th...


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PLL103-02 General Description


The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 also has an I2C interface, which can enable or disable each output clock. When power up, all output clocks are enabled (has internal pull up).

PLL103-02 Maximum Ratings

PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VSS-0.5
7.0
V
Input Voltage, dc
VI
VSS-0.5
VDD+0.5
V
Output Voltage, dc
VO
VSS-0.5
VDD+0.5
V
Storage Temperature
TS
-65
150
Ambient Operating Temperature
TA
0
70
ESD Voltage  
2
KV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this  pecification is not implied.

PLL103-02 Features

· Supports up to four DDR DIMMS or 2 SDRAM DIMMS.
· Supports 266MHz DDR SDRAM.
· One additional output for feedback.
· Less than 5ns delay.
· Skew between any outputs is less than 100 ps.
· 2.5V or 3.3V Supply range.
· Enhanced DDR and SDRAM Output Drive selected by I2C.
· Available in 48 pin SSOP.

PLL103-02 Connection Diagram

PLL103-02  Connection Diagram

PLL103-02 datasheet

PLL103-02
PDF/DataSheet Download

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