Pm25LV512 General Description
Pm25LV512 Features
•Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
• Memory Organization
- Pm25LV512: 64K x 8 (512 Kbit)
- Pm25LV010: 128K x 8 (1 Mbit)
•Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 32 Kbyte blocks (8 sectors per block)
- Two blocks with 32 Kbytes each (512 Kbit)
- Four blocks with 32 Kbytes each (1 Mbit)
- 128 pages per block
• Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
• High Performance Read
- 25 MHz clock rate (maximum)
• Page Mode for Program Operations
- 256 bytes per page
• Block Write Protection
- The Block Protect (BP1, BP0) bits allow part or entire of the memory to be configured as read-only.
• Hardware Data Protection
- Write Protect (WP#) pin will inhibit write operations to the status register
• Page Program (up to 256 Bytes)
- Typical 2 ms per page program time
• Sector, Block and Chip Erase
- Typical 40 ms sector/block/chip erase time
• Single Cycle Reprogramming for Status Register
- Build-in erase before programming
•High Product Endurance
- Guarantee 100,000 program/erase cycles per single sector (preliminary)
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin JEDEC SOIC
- 8-contact WSON
- Optional lead-free (Pb-free) packages
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