SAA7158

The Back END IC (abbreviated as BENDIC)SAA7158 is designed to cooperate with an 8051 type of microprocessor, the ECO3 (SAA4951) memory controller and Texas Instruments TMS4C2970 memories, but other configurations may be applicable. Fig.1 shows the block diagram of the feature box. The nominal clock frequency of the IC is 27 MHz or 32MHz, with a maximum of 36 MHz.

The SAA7158 supports the digital Y/U/V bus for selection of different video signal sources. The Y/U/V bus and the BENDIC data input are fully synchronous with respect to the clock signal. A line reference signal BLN for timing control purposes SAA7158 has to be provided by external elements which always controls the system timing, independent of active signal sources or desired functions.