SDA5523

The on-chip clock generator SDA5523 provides the TVTpro with its basic clock signal. The oscillator runs with an external crystal and the appropriate internal oscillator circuitry (see Fig. on page 174).

For applications of SDA5523 with lower timing accuracy requirements (and if the RTC is not used) an external ceramic resonator can be used. The usage of a ceramic resonator is not recommended for Teletext applications as depending on the absolute tolerance of the ceramic resonator the data slicer may not work correctly. Additional SDA5523 might also require that display timing parameters and the baud rate prescaler have to be adapted.

In timing critical applications the horizontal frequency of the incoming CVBS signal of SDA5523 can be used to measure the actual timing deviation and to re-program the clock PLL.

The 6 MHz clock signal is used to generate the internal 300 MHz display reference clock by means of an onchip phase locked loop (PLL). The PLL SDA5523 can be bypassed to reduce the power consumption. If an immediate wake up from power down is not required the PLL SDA5523 can also be switched off in this mode. From the output frequency of the main clock PLL two clock systems are derived.