SDA9251-2X

The SDA 9251 is a triple port 868 352 bit dynamic sequential-access memory for high-data-rate video applications. It is organized as 212 rows by 64 columns by 16 arrays by 4 bit to allow for the storage of 4-bit planes of a TV field (NTSC, PAL, SECAM, MAC) in standard or studio quality (13.5-MHz basic sample rate) or 4-bit planes of parts of a HDTV field. The memory is fabricated using the same CMOS technology used for 1-Mbit standard dynamic random access memories.

The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit length and 4-bit width, which perform a serial to parallel conversion between the asynchronous input/output data streams and the memory array. The parallel data transfer from the 16 x 4-bit input shift register C to an addressed location of the memory array and from the memory array to one of the 16 x 4-bit output shift registers A or B is controlled by the serial column address (SAC) which contains the desired column address and an instruction code (mode bits) for transfer and refresh.