SDA9257

Multi-standard operation (50 Hz, 60 Hz; PAL, NTSC, SECAM)
 Vertical noise suppression and 50/60-Hz detection
 Serial digital output for actual frequency value and CVBS-black level
 All settings made by I2C Bus
PLL lock-in behavior can be set to TV- or VCR mode
 Automatic clamping of CVBS input
Provides all horizontal and vertical sync signals and clocks for operating PAMUX, analog color decoders, the  A/D  converters, PSND and Featurebox
Free-running capability
Frequency generator function possible with digitally adjustable frequency
 Lock-in function of the PLL on CVBS also possible with externally supplied 24-MHz or 27-MHz clock

The clock sync generator SDA9257 consists essentially of the following function blocks (refer to block diagram):
Analog clamping
7-bit, 27-MHz A/D converter
Sync processor with digital horizontal PLL, vertical sync processor and pulse generator
Clock generator with discrete timing oscillator, D/A converter, analog PLL and divider, as well as a crystal oscillator
I²C Bus interface
Button flutter elimination