SDA9288X

• Single chip solution
Clamping, AD conversion, filtering, field memory, RGB matrix, DA-conversion and clock generation integrated on one chip
• 2 picture sizes
1/9 or 1/16 of normal size
• High resolution display
13.5 MHz/27 MHz display clock frequency
212 luminance and 53 chrominance pixels per inset line for picture size 1/9
6-bit amplitude resolution for each incoming signal component
Field and frame mode display
Horizontal and vertical filtering
Special antialias filtering for the luminance signal
• 16:9 compatibility
Operation in 4:3 and 16:9 sets
4:3 inset signals on 16:9 displays or v.v. with picture size 1/9 and 1/16, respectively
• Analog inputs
Y, + (B-Y), + (R-Y) or Y, -(B-Y), -(R-Y)
• Analog outputs
Y, + (B-Y), + (R-Y) or Y, (B-Y), (R-Y) or RGB
3 RGB matrices: EBU, NTSC (Japan), NTSC (USA)
• Free programmable position of inset picture
Steps of 1 pixel and 1 line
All PIP and POP positions are possible
• Programmable framing
4096 frame colors
Variable frame width
• Freeze picture
• I2C Bus control
• Threefold PIP/POP facility
Three different I2C-addresses (pin-programmable)
Tri-State outputs
• Numerical PLL circuit for high stability clock generation
• No necessity of PAL/SECAM delay lines
(using suitable color decoders i.e. TDA 8310)
• Multistandard applications
625 lines/525 lines standard (inset and parent channel)
Scan conversion systems as flickerfree display systems (parent channel)
HDTV (parent channel)
• P-DSO-32-2 package/350 mil (SMD)
• 5 V supply voltage