SDA9361

• Deflection - Protection - 16:9 / 4:3
• No external clock needed
• 1 PLL and 2 PLL on chip
• I²C-Bus alignment of all deflection parameters
• All EW-, V- and H- functions
• PW EHT compensation
• PH EHT compensation
• Compensation of H-phase deviation (e.g. caused by white bar)
• Upper/lower EW-corner correction separately adjustable
• V-angle correction: Vertical frequent linear modulation of H-phase
• V-bow correction: Vertical frequent parabolic modulation of H-phase
• Three reduced V-scan modes (75 %, 66 %, 50 % V-size) adjustable by only 2 Bits
• H-frequent PWM output signal for general purpose
• H- and V-blanking time adjustable
• Partial overscan adjustable to hide the cut off control measuring lines in the reducedscan modes
•Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different letterbox formats without    annoying overscan
• Control signal SCAN as reference for vertical positioning of OSD, PIP etc.
• Vertical noise reduction with memory
• Standard and doubled line frequencies for NTSC and PAL, MUSE standard, ATV standard, HDTV standard
• Self adaptation of V-frequency/number of lines per field between 192 and 680 for each possible line frequency
• Protection against EHT run away (X-rays protection)
• Protection against missing V-deflection (CRT-protection)
• Selectable softstart of the H-output stage
• Clock generation on chip
• P-MQFP-44-2 package
• 5 V supply voltage

The SDA 9361 is a highly integrated deflection controller for CTV receivers with standard or doubled line and field frequencies. It controls among others an horizontal driver circuit for a flyback line output stage, a DC coupled vertical saw-tooth output stage and an east/ west raster correction circuit. All adjustable output parameters are I2C Bus controlled. Inputs of SDA 9361 are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock system which includes the F1 and F2 control loops.